5962-9467201QXA

5962-9467201QXA description

The SN54ABT18502 scan test device with 18-bit universal bus transceiver is a member of the Texas InstrumentsSCOPE testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry isaccomplished via the 4-wire test access port (TAP) interface.In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-typeflip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bittransceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samplesof the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAPin the normal mode does not affect the functional operation of the SCOPE universal bus transceiver.Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode whenLEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, theB outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow issimilar to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.In the test mode, the normal operation of the SCOPE  universal bus transceivers is inhibited and the testcircuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitryperforms boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test dataoutput (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testingfunctions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.Additional flexibility is provided in the test mode through the use of two boundary-scan cells (BSCs) for eachI/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNTinstruction also is included to ease the testing of memories and other circuits where a binary count addressingscheme is useful.The SN54ABT18502 is characterized for operation over the full military temperature range of – 55°C to 125°C.