SN74GTLP22034GQLR

SN74GTLP22034GQLR description

The SN74GTLP22034 is a high-drive, 8-bit, three-wire registered transceiver that provides true LVTTL-to-GTLPand GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes ofdata transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control anddiagnostics monitoring, the same functionality as the SN74FB2033, but with true logic. The device provides ahigh-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signallevels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct resultof GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OECcircuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and havebeen designed and tested using several backplane models. The high drive allows incident-wave switching inheavily loaded backplanes with equivalent load impedance down to 11 Ω.The AO outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshootand undershoot.

SN74GTLP22034GQLR description (continued)

GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.The ac specification of the SN74GTLP22034 is given only at the preferred higher noise-margin GTLP, but theuser has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 Vand VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TIapplication reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, andGTLP in BTL Applications, literature number SCEA017.Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,but are 5-V tolerant and can be directly driven by TTL or 5-V CMOS devices. VREF is the B-port differential inputreference voltage.This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powereddown. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and powerdown, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-portinput/output connections, preventing disturbance of active data on the backplane during card insertion orremoval, and permits true live-insertion capability.This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminatedbackplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improvessignal integrity, which allows adequate noise margin to be maintained at higher frequencies.High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERCinput voltage between low and high adjusts the B-port output rise and fall times. This allows the designer tooptimize system data-transfer rate and signal integrity to the backplane load.When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.However, to ensure the high-impedance state above 1.5 V, OEAB should be tied to VCC through a pullup resistorand OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor isdetermined by the current-sinking/current-sourcing capability of the driver.

SN74GTLP22034GQLR functional description

The SN74GTLP22034 is a high-drive (100 mA), 8-bit, three-wire registered transceiver containing D-typelatches and D-type flip-flops for data-path operation in the transparent, latched, or flip-flop modes. Datatransmission is true, with AI data going to the B port and B data going to AO. The split LVTTL AI and AO providesa feedback path for control and diagnostics monitoring.The logic element for data flow in each direction is configured by two mode (IMODE1 and IMODE0 for B to A,OMODE1 and OMODE0 for A to B) inputs as a buffer, a D-type flip-flop, or a D-type latch. When configured inthe buffer mode, the input data appears at the output port. In the flip-flop mode, data is stored on the rising edgeof the appropriate clock (CLKAB/LEAB or CLKBA/LEBA) input. In the latch mode, the clock inputs serve asactive-high transparent latch enables.Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by theLOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, theoutput of the selected A-to-B logic element is the B-to-A input.The AO enable/disable control is provided by OEBA. When OEBA is low or when VCC is less than 1.5 V, AOis in the high-impedance state. When OEBA is high, AO is active (high or low logic levels).The B port is controlled by OEAB and OEAB. If OEAB is low, OEAB is high, or VCC is less than 1.5 V, the B portis inactive. If OEAB is high and OEAB is low, the B port is active.The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logicelements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associatedoutputs are in the high-impedance (AO) or inactive (B port) states.