5962-8860601EA

5962-8860601EA Features

• Select One of Eight Data Outputs- Active Low for CD74HC137 and CD74HCT137- Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V,15pF, TA = 25oC (CD74HC237) • Fanout (Over Temperature Range)- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTLLogic ICs • HC Types- 2V to 6V Operation- High Noise Immunity: NIL = 30%, NIH = 30%, of VCCat VCC = 5V • HCT Types- 4.5V to 5.5V Operation- Direct LSTTL Input Logic Compatibility,VIL= 0.8V (Max), VIH = 2V (Min)- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

5962-8860601EA Description

TheCD74HC137,CD74HCT137,’HC237,andCD74HCT237 are high speed silicon gate CMOS decoderswell suited to memory address decoding or data routingapplications. Both circuits feature low power consumptionusually associated with CMOS circuitry, yet have speedscomparable to low power Schottky TTL logic.Both circuits have three binary select inputs (A0, A1 and A2)that can be latched by an active High Latch Enable (LE)signal to isolate the outputs from select-input changes. A“Low” LE makes the output transparent to the input and thecircuit functions as a one-of-eight decoder. Two OutputEnable inputs (OE1 and OE0) are provided to simplifycascadingandtofacilitatedemultiplexing.Thedemultiplexing function is accomplished by using the A0, A1,A2 inputs to select the desired output and using one of theother Output Enable inputs as the data input while holdingthe other Output Enable input in its active state. In theCD74HC137 and CD74HCT137 the selected output is a“Low”; in the ’HC237 and CD74HCT237 the selected output isa “High”.