80KSW0002ALGI8

80KSW0002ALGI8 2 Features

–Interfaces - sRIO–– Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps– All lanes support short haul or long haul reach for each PHY speed– Configurable port count to up to sixteen 1x ports, four 4x ports, or– Support for two separate port rates for each quad– Supports standard 4 levels of priority– Error management supportInterfaces - I2C– Provides I2C port for maintenance and error reporting– Master or Slave Operation– Master allows power-on configuration from external ROM– Master mode configuration with external image compressing and–– Non-blocking data flow architecture within each sRIO priority– Very low latency for all packet length and load condition–– Standard receiver based physical layer flow control– Configurable for Cut Through or Store And Forward data flow– Device configurable through any of sRIO ports, I2C, or JTAG– Packet Trace. Each port provides the ability to match the first 160 bits– Packet Filter. Each port also provides the ability to filter the packet– Supports up to 10 simultaneous multicast masks– Broadcast support– Port Loopback Debug Feature– Software assisted error recovery, supporting hot swap–––––– Package: 324-ball grid array, 19mm x 19mm, 1.0mm ball pitch––

80KSW0002ALGI8 4 Device Description

The CPS-16 is optimized for DSP cluster applications at board level. Its main function is to have a backplane interface which can connect to a back-plane switch or directly to multiple RF cards. On the line card side it can also connect to multiple ports. It supports up to 16 ports which are configu-rable as line card, or backplane ports. It is an end-point free (switch) device in an sRIO network.The CPS-16 receives packets from up to 16 ports. The CPS offers full support for normal switching as well as enhanced functions:1) Normal Switching: All packets are switched in accordance with standard serial RapidIO specifications, with packet destination IDs determininghow the packet is routed.Three major options exist within this category:b. Unicast: All other operations are performed as specified in sRIO.c. Maintenance packets: As specified by sRIO.The sRIO Switch supports a peak throughput of 40 Gbps which is the line rate for 16 ports in 1x configuration, each at 2.5 Gbps (3.125 Gbps minusthe sRIO-defined 8b10b encoding), and switches dynamically in accordance with the packet headers and priorities.2) Enhanced functionsEnhanced features are provided for support of system debug. These features which are optional for the user consist of two major functions:a. Packet Trace: The Packet Trace feature provides at-speed checking of the first 160 bits (header plus a portion of any payload) of every incom-ing packet against user-defined comparison register values. The trace feature is available on all serial RapidIO ports, each acting inde-pendently from one another. If the trace feature is enabled for a given port, every incoming packet is checked for a match against up to 4comparison registers. In the event of a match, either of two possible user defined actions may take place:i) not only does the packet route normally through the switch to its appropriate destination port, but this same packet is replicated and sent toa “trace port.” The trace port itself may be any of the standard serial RapidIO ports. The port used for the trace port is defined by the userthrough simple register configuration.ii) the packet is dropped.If there is no match, the packets route normally through the switch with no action taken.The Packet Trace feature can be used during system bring-up and prototyping to identify particular packet types of interest to the user. It mightbe used in security applications, where packets must be checked for either correct or incorrect tags in either of the header or payload. Identi-fied (match) packets are then routed to the trace port for receipt by a host processor, which can perform an intervention at the software level.b. Port Loopback: The CPS-16 offers internal loopback for each port that may be used for system debug of the high speed sRIO ports. Byenabling loopback on a given port, packets sent to the port’s receiver are immediately looped back at the physical layer to the transmitter -bypassing the higher logical or transport layers.c. Broadcast: Each multicast mask can be configured so that the source port is included among the destination ports of that multicast operation.The CPS-16 can be programmed through any one or combination of sRIO, I2C, or JTAG. Note that any sRIO port may be used for programming. TheCPS-16 can also configure itself on power-up by reading directly from ROM over I2C in master mode.

80KSW0002ALGI8 5 Applications

Central switch based wireless processingNote: The CPS-16 provides direct support for backplane connections using the serial RapidIO standard. The addition of an appropriate bridge (e.g.,CPRI  sRIO) allows for further backplane flexibility, accommodating designs based on a wide range of standards such as CPRI, OBSAI, GbE orPCIe.In a macro wireless station, a switch-based raw data combination and distribution architecture is widely adopted. Switch based architecture provideshigh flexibility and high resource efficiency. The raw data from the Radio Unit is distributed to one or more processing cards by unicast or multicast.Aggregating raw data from processing cards to a buffer-less chain can be done by a fast non-blocking switch.Media Gateway and general processingNote: The CPS-16 provides direct support for backplane connections using the serial RapidIO standard.Though SAR and RTP is usually processed by NP/Processor, DSP is more efficient for TDM conversion and compression. A low jitter switch enablesthe full utilization of DSP processing power. Priority support, fast switching, and multicasting will differentiate class of traffic to provide QoS.