SSTUG32868ET/G,518

SSTUG32868ET/G,518 2. Features

SSTUG32868ET/G,518 1. General description

The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rankby four (2R · 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. Itis similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates thefunctionality of the normally required two registers in a single package, thereby freeing upboard real-estate and facilitating routing to accommodate high-density Dual In-lineMemory Module (DIMM) designs.The SSTUG32868 also integrates a parity function, which accepts a parity bit from thememory controller, compares it with the data received on the D-inputs and indicateswhether a parity error has occurred on its open-drain QERR pin (active LOW).It further offers added features over the JEDEC standard register in that it is permanentlyconfigured for high output drive strength. This allows use in high density designs withheavier than normal net loading conditions. Furthermore, the SSTUG32868 features twoadditional chip select inputs, which allow more versatile enabling and disabling in denselypopulated memory modules. Both added features (drive strength and chip selects) arefully backward compatible to the JEDEC standard register. Finally, the SSTUG32868 isoptimized for the fastest propagation delay in the SSTU family of registers.The SSTUG32868 is packaged in a 176-ball, 8 · 22 grid, 0.65 mm ball pitch, thin profilefine-pitch ball grid array (TFBGA) package, which (while requiring a minimum6 mm · 15 mm of board space) allows for adequate signal routing and escape usingconventional card technology.n 28-bit data register supporting DDR2n Fully compliant to JEDEC standard for SSTUB32868n Supports 2 rank by 4 DIMM density by integrating equivalent functionality of twoJEDEC-standard DDR2 registers (that is, 2 · SSTUA32864 or 2 · SSTUA32866)n Parity checking function across 22 input data bitsn Parity out signaln Controlled multi-impedance output impedance drivers enable optimal signal integrityand speedn Meets or exceeds SSTUB32868 JEDEC standard speed performancen Supports up to 450 MHz clock frequency of operationn Permanently configured for high output driven Optimized pinout for high-density DDR2 module designn Chip-selects minimize power consumption by gating data outputs from changing state

SSTUG32868ET/G,518 DDR2-1G RDIMM applications

Rev. 01 — 23 April 2007Product data sheet

SSTUG32868ET/G,518 3. Applications

n 400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMsn DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality