74AXP1G97GS125

74AXP1G97GS125 2. Features and benefits

•Wide supply voltage range from 0.7 V to 2.75 V •Low input capacitance; CI = 0.5 pF (typical) •Low output capacitance; CO = 1.0 pF (typical) •Low dynamic power consumption; CPD = 2.6 pF at VCC = 1.2 V (typical) •Low static power consumption; ICC = 0.6 μA (85 °C maximum) •High noise immunity •Latch-up performance exceeds 100 mA per JESD 78 Class II •Inputs accept voltages up to 2.75 V •Low noise overshoot and undershoot < 10 % of VCC •IOFF circuitry provides partial power-down mode operation •Complies with JEDEC standard: •JESD8-12A.01 (1.1 V to 1.3 V) •JESD8-11A.01 (1.4 V to 1.6 V) •JESD8-7A (1.65 V to 1.95 V) •JESD8-5A.01 (2.3 V to 2.7 V) •ESD protection: •HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V •CDM JESD22-C101E exceeds 1000 V •Multiple package options •Specified from -40 °C to +85 °C

74AXP1G97GS125 1. General description

The 74AXP1G97 is a configurable multiple function gate with Schmitt-trigger inputs. The devicecan be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverterand buffer. All inputs can be connected directly to VCC or GND.This device ensures very low static and dynamic power consumption across the entire VCC rangefrom 0.7 V to 2.75 V. This device is fully specified for partial power down applications using IOFF.The IOFF circuitry disables the output, preventing the potentially damaging backflow current throughthe device when it is powered down.

74AXP1G97GS125 6.2. Pin description

Table 3. Pin descriptionSymbolPinDescriptionB1data inputGND2ground (0 V)A3data inputY4data outputVCC5supply voltageC6data input